從電晶體到 CPU
前言
電腦是怎麼「思考」的？ 你可能知道 CPU 是電腦的「大腦」，但這個大腦到底是怎麼運作的？本章帶你從最基層的電晶體開始，一步步理解 CPU 的建構原理。
這篇文章會帶你學什麼？
學完這章後，你將獲得：
- 術語理解能力：聽到「CPU 主頻」、「多核」、「指令集」不再一頭霧水
- 程式碼執行視角：看到一行程式碼如何經過取指、解碼、執行、寫回
- 抽象層次思維：理解每一層如何向上層提供服務
- 後續學習基礎：為電腦體系結構、嵌入式開發打下基礎
| 章节 | 內容 | 核心概念 |
|---|---|---|
| 第 1 章 | 電晶體 | 數位世界的開關 |
| 第 2 章 | 邏輯閘 | 布林運算的物理實作 |
| 第 3 章 | 功能單元 | 加法器、暫存器、多工器 |
| 第 4 章 | CPU 核心 | 取指、解碼、執行、寫回 |
0. 全景圖：從沙子到智慧
在探索電腦底層的過程中，常常會遇到一個最根本的問題：現代電腦的「思考」能力，究竟從何而來？
答案是一個再簡單不過的物理抽象：開關。
想象你面前有一個控制燈泡的開關。按下燈亮，表示為「1」；斷開燈滅，表示為「0」。如果我們擁有幾十億個這樣的開關，並且能夠讓一個開關的輸出去控制另一個開關，從而組合無比複雜的邏輯網路，會發生什麼？
答案是一台能執行任意邏輯的通用運算平台。
逐層解構：從沙子到智慧
- 第一層：電晶體（數百億級） — 最底層的「開關」
- 第二層：邏輯閘（數十億級） — 電路變成了數學
- 第三層：功能單元（數百級） — 有特定用途的運算模組
- 第四層：CPU 核心（1-128核） — 整個微架構的指揮中心
1. 電晶體：數位世界的開關
MOSFET transistor diagram -- click to toggle Gate voltage
Source
Source
Source
Gate0
Open -> output 0
Drain
Drain
Drain
👆 Click to toggle Gate voltage
1.1 什麼是電晶體？
概念引入
電晶體（Transistor） 是一種改變了人類歷史的半導體元件。在數位電路的語境下，我們可以直接把它抽象為一個完美的「開關」。
電晶體其實就是一個奈米級的水龍頭：
- 源極 (Source) 和 汲極 (Drain) 就如同水管的兩端。
- 閘極 (Gate) 就是那個用來控制水流的閥門。
關鍵的區別在於：我們不是用手去擰開關，而是用電壓訊號。
1.2 電晶體如何表示 0 和 1？
- 我們把高電壓（比如 3.3V 或 1.0V） 定義為邏輯的 1（True）。
- 把低電壓（接近 0V） 定義為邏輯的 0（False）。
1.3 電晶體數量的演進
| 時代標誌 | 處理器晶片 | 電晶體數量 | 製程節點 |
|---|---|---|---|
| 1971 | Intel 4004 | 2,300 | 10微米 |
| 1993 | Intel Pentium | 310萬 | 800奈米 |
| 2006 | Intel Core 2 Duo | 2.91億 | 65奈米 |
| 2020 | Apple M1 | 160億 | 5奈米 |
| 2023 | Apple M3 Max | 920億 | 3奈米 |
2. 邏輯閘：用開關做運算
2.1 從電晶體到邏輯閘
Four Basic Logic GatesThe building blocks of all digital computing
ANDAND gate
Operation:
A ∧ BOutputs 1 only when both inputs are 1
Series switches: both switches must be closed
Truth table
| A | B | Output |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
OROR gate
Operation:
A ∨ BOutputs 1 when at least one input is 1
Parallel switches: either switch can close the circuit
Truth table
| A | B | Output |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
NOTNOT gate
Operation:
¬AInverts the input: 0 becomes 1, 1 becomes 0
Inverter: on becomes off, off becomes on
Truth table
| A | Output |
|---|---|
| 0 | 1 |
| 1 | 0 |
XORXOR gate
Operation:
A ⊕ BOutputs 1 only when the two inputs are different
Difference detector: different means true
Truth table
| A | B | Output |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Core idea: Logic gates turn physical circuit on/off states into mathematical true/false operations. They are the bridge from hardware to software logic.
2.2 基本邏輯閘介紹
- AND 閘（與閘）：只有當所有輸入都為 1 時，輸出才為 1。如同開啟銀行金庫，必須經理和主管同時插入各自的鑰匙。
- OR 閘（或閘）：只要有一個輸入為 1，輸出就為 1。
- NOT 閘（非閘 / 反相器）：輸入 1 必定輸出 0，輸入 0 必定輸出 1。
- XOR 閘（互斥或閘）：當兩個輸入不相同時，輸出恰好為 1。
2.3 用邏輯閘實作加法
From Hand Addition to Logic GatesHow can computers do math with only 0 and 1? Follow the pattern.
Step 1: Recall carrying in decimal addition
1
7
+5
12
Because 7 + 5 = 12, the result is larger than the largest single digit (9). We split 12 into "one full 10" and "the remaining 2":
- 2 The remaining 2 stays in the current column. This is the sum bit.
- The full 10 carries a 1 into the tens column. This is the carry.
Step 2: The four binary addition cases
+=00
0 + 0 = 0. Write 0 in this column, with no carry.
Step 3: Name the patterns as circuits
ABCarrySum
0000
0101
1001
1110
Sum Sum pattern:
The sum is 1 only for inputs (0,1) or (1,0). It is 1 only when the two inputs are different.
In circuits, this pattern is called XOR.
Carry Carry pattern:
The carry is 1 only for inputs (1,1). It is 1 only when both inputs are 1.
In circuits, this pattern is called AND.
把一個 XOR 閘（負責算本位）和一個 AND 閘（負責算進位）組合起來，就得到了半加器（Half Adder）。
Half Adder -- Interactive DemoClick inputs A and B to see the result for one binary column
+=00
▲ Carry: pass a 1 to the column on the left ▲ Sum: the digit written in this column
0 + 0 = 0. Write 0 in this column, with no carry.
All possible cases
ABWrite (sum)Carry
0000
0110
1010
1101
Look closely at the table and two patterns appear:
- The sum column is 1 only when A and B are different. This is XOR.
- The carry column is 1 only when A and B are both 1. This is AND.
The circuit is connected like this:
A = 0
B = 0
XOR gate
Different -> 1
Output: 0
AND gate
All 1 -> 1
Output: 0
Sum
0
0
Carry
0
0
半加器有個致命缺陷：它只有兩個輸入埠（A 和 B）。為了解決這個問題，我們需要能接收三個訊號的全加器（Full Adder）：
Full Adder -- Interactive DemoA full adder adds one more input: carry-in (Cin) from the lower bit. Click the three inputs to try it.
++=01
ABCarry-inCarrySum
1 + 0 + 0 = 1. Write 1 in this column, with no carry.
Compared with a half adder: A full adder adds a third input: carry-in (Cin). In multi-bit addition, each column adds A, B, and the carry from the column on the right.
All 8 cases (3 inputs -> 2³ = 8)
ABCinSumCarry
00000
00110
01010
01101
10010
10101
11001
11111
Inside a full adder = two half adders in series
Step 1: Half adder 1
First calculate A + B
A = 1B = 0
→
Intermediate sum: 1Carry 1: 0
▸
Step 2: Half adder 2
Add the intermediate sum and carry-in
Intermediate sum = 1Cin = 0
→
Sum: 1Carry 2: 0
▸
Step 3: Merge carries
If either carry path is 1, carry 1 into the next higher bit.
Carry 1 = 0Carry 2 = 0
→
Final carry: 0
把多個全加器級聯起來，就能完成多位數的加法：
Ripple Carry AdderCascade multiple full adders to perform multi-bit binary addition
CascadeLower-bit Cout connects to higher-bit Cin
RippleCarry propagates bit by bit like a wave
OverflowThe highest bit produces a carry beyond the range
Bits:
+=13
A0111(7)
B0110(6)
=1101(13)
Adder cascadeHover to inspect each bit calculation
Bit 0Half adder
A1B0
Sum1Cout0
Bit 1Full adder
A1B1Cin0
Sum0Cout1
Bit 2Full adder
A1B1Cin1
Sum1Cout1
Bit 3Full adder
A0B0Cin1
Sum1Cout0
Overall calculation
Input:A = 7 (0111), B = 6 (0110)
Process:Start at bit 0, compute each sum and carry, and propagate carries toward higher bits.
Result:1101 = 13
Core idea: Carry ripples from the lowest bit to the highest bit, which is why this circuit is called a ripple carry adder. More bits increase delay, but the circuit stays simple.
Complete Adder DemoFrom logic gates to multi-bit addition -- abstraction layer by layer
Layer 1: Logic gates
The basic operation units. Each gate performs one Boolean operation.
AND gateOutputs 1 only when all inputs are 1
OR gateOutputs 1 when any input is 1
XOR gateOutputs 1 when inputs differ
&
AND gateA AND B
0001
>=1
OR gateA OR B
0111
=1
XOR gateA XOR B
0110
1
NOT gateNOT A
10
Core idea: Logic gates turn voltage levels (0/1) into Boolean operations (false/true). They are where hardware starts implementing math.
Abstraction layers
Logic gates
→Half adder
→Full adder
→Multi-bit adder
→ALU/CPU
3. 功能單元：邏輯閘的組合
| 模組名稱 | 承擔的核心使命 | 現實生活中的絕佳隱喻 |
|---|---|---|
| 加法器 | 處理算術運算引擎 | 不知疲倦的算盤 |
| 多工器(MUX) | 控制資料流向 | 鐵路線上的精密道岔 |
| 解碼器 | 翻譯二進位指令 | 破獲密電的翻譯員 |
| 正反器 | 記錄歷史狀態 | 會保持狀態的蹺蹺板 |
Common Functional Units -- switch modules to see how they work
Multiplexer (MUX): like a railway switch, it uses the select signal to decide which data input passes through.
Data 0 (D0)
Data 1 (D1)
MUX
Select (Sel)
Output (Out)0
The select signal is 0, so the output equals data 0 (D0): 0
CPU Register FileHigh-speed storage inside the CPU
Special Registers
PC
0x00401000
Program counter
IR
0x8B450008
Instruction register
MAR
0x00401000
Memory address register
MDR
0x00000000
Memory data register
ACC
0x0000001A
Accumulator
General Purpose Registers
RAX
0x00000000
Return value
RBX
0x00000000
Base register
RCX
0x00000000
Counter register
RDX
0x00000000
Data register
RSI
0x00000000
Source index
RDI
0x00000000
Destination index
RBP
0x00000000
Base pointer
RSP
0x7FFDE000
Stack pointer
Program Status Word (PSW / FLAGS)
CF0Carry flag
PF0Parity flag
AF0Auxiliary carry
ZF0Zero flag
SF0Sign flag
OF0Overflow flag
Registers vs Memory
| Feature | Register | Memory (RAM) |
|---|---|---|
| Location | Inside the CPU | Outside the CPU |
| Access speed | Fastest (< 1ns) | Slower (50-100ns) |
| Capacity | Tiny (bytes) | Large (GB) |
| Role | Hold instructions, operands, and results | Store programs and data |
3.2 暫存器：資料的儲存單元
深入理解：記憶本質上是一種循環
要產生持續的「記憶」，早期的先驅者想到了一個絕妙的設計：將輸出的電波重新回饋到輸入端。
當我們將 32 個或 64 個正反器整齊地編排成一列，施加同一種強勁的時脈頻率訊號來號令它們統一行動時，暫存器（Register） 便應運而生。
From Flip-Flops to Registers: The Feedback Loop of Memory
Change the data and observe it: without a clock signal, the output feeds back to the input and the closed loop preserves memory.
Data Bus (Data Input)
1
0
1
0
Gate
4-bit Register (Stored State)
0
0
0
0
Control Center
Try changing the left-side input. The register value is locked while the feedback loop is closed.
4. CPU 架構：從功能單元到處理器
4.1 CPU 的核心組件
- 算術邏輯單元 (ALU)：負責「幹活」的運算單元
- 暫存器組 (Register File)：工作台上的臨時抽屜
- 內部匯流排 (Internal Bus)：系統裡的傳送帶
- 控制單元 (Control Unit)：總指揮
CPU Internal Microarchitecture
Click a module to see its subcircuits and how it works
CPU Core (Central Processing Unit)
Address Bus
Data Bus
Control Unit
Program Counter (PC)
Instruction Register (IR)
Instruction Decoder
Clock Generator
Control signals ↓
Register File
General Registers R0-R3
Accumulator (ACC)
Arithmetic Logic Unit (ALU)
Adder Circuit
Status Flags
Control Bus
Click a module in the CPU diagram to explore its circuit-level implementation.
4.2 CPU 是如何執行指令的？
- 取指 (Fetch)：按照程式計數器的位址，從快取中取出下一條指令
- 解碼 (Decode)：分析這道命令具體要做什麼
- 執行 (Execute)：指令到達 ALU 等運算單元執行
- 寫回 (Write Back)：將結果寫至特定的暫存器或記憶體
Detailed CPU Instruction Cycle Demo
CPU
Control Unit CU
PC256Program Counter
IR—Instruction Register
MAR—Memory Address Register
MDR—Memory Data Register
Arithmetic Logic Unit ALU
ACC0Accumulator
—
General Register File
R00
R10
R20
R30
Address Bus
Data Bus
Control Bus
→
↔
→
Main Memory
▶0x100LOAD R0, [0x200]
0x101LOAD R1, #7
0x102ADD R0, R1
0x103STORE [0x201], R0
Data Area
0x51242
0x5130
Step 0 / 32
Click "Clock Pulse" to step through execution, or "Auto Run" to play continuously.
追求效率的極致：流水線（Pipeline）
晶片工程師引入了指令流水線技術。當第一部分電路在對指令 A 進行「執行」時，之前的電路並沒有閒著，而是去對指令 B 進行「解碼」，甚至是把指令 C 提前「取指」拿出來。
5. 總結：跨越抽象層級
- 巨觀物理：沙子（二氧化矽晶體）
- 微觀物理：海量的電晶體開關
- 數位代數：AND / OR / NOT 邏輯閘體系
- 微架構模組：功能單元積木集
- 複雜體系架構：CPU 聯合陣列
- 萬千應用王國：演算法、系統軟體以及網際網路
電腦科學中最令人著迷的部分在於，每一層封裝都完美地隱藏了下一層的複雜細節。
終極思考
歸根究底，所謂的算力，不過是有限的密閉空間內海量開關重組的變幻；伴隨著時脈的節拍，在這片小小的矽片上完成了複雜的運算。
延伸閱讀
- 經典教材：《電腦組成與設計（軟硬體介面）》
- 數位邏輯模擬：嘗試使用邏輯模擬軟體搭建一個簡單的 8 位元加法器
- 底層與組合語言：嘗試學習一些基礎組合語言